Avago Technologies Front End IC Design Engineer in Santa Clara, California


The Processor division of Broadcom Limited is well known in the semiconductor industry for providing high-performance multi-core CPU SOCs. We are staffing up in critical R&D; areas for our next generation high performance Multi-CPU Server SOC in our Santa Clara and Austin design centers. As a member of the RTL/Logic design team, you will be responsible for performing micro-architecture and logic design for one of the SOC component areas. The areas include high performance CPU design, DDR memory controllers and interfaces, high performance Serial I/O Controllers and Serdes including PCIe and Inter-chip Coherent interfaces, Memory/Cache Coherency within and across multiple chips, Network and Acceleration solutions


  • Develop micro-architecture specification for one of CPU, Memory, Cache, I/O, Acceleration or Network Subsystems
  • Implement the RTL code for the unit
  • Collaborate with verification team in the development of Testplan, Testbench and Tests; and assist in debugging of test failures in simulation and emulation environments
  • Support physical design team in writing timing constraints, analyze timing violations and perform timing fixes in RTL.
  • Own and drive future design of additional system blocks
  • Total engineering minimum experience required is typically a BS degree and 14 years of experience, an MS degree and 12 years of experience or a PhD and 9 years of experience
  • MSEE or MSCS preferred
  • Must have working knowledge of Verilog, pipelining, various flow control methods

We are an Equal Opportunity Employer and do not discriminate against applicants due to male, female, veterans status or on the basis of disability.


Job: R&D;

Primary Location: United States-California-Santa Clara

Other Locations: United States-Texas-Austin

Organization: PDO

Schedule: Full-time

Job Posting: Jun 13, 2016, 4:50:32 PM

Unposting Date: Ongoing

Req ID: 161157