Avago Technologies DFT Engineer in Santa Clara, California

Description

This position will be responsible for all aspects of advanced DFT implementations in various chip projects. This will involve improvements in the DFT automation infrastructure, detailed understanding of DFT hardware, ATPG process, scan compression, MBIST, STA constraints for various DFT modes, independent problem solving debugging various simulation failures, formal verification, DC TCL knowledge, Perl knowledge, etc.

Qualifications

B.S. degree and minimum of 5 years experience

We are an Equal Opportunity Employer and do not discriminate against applicants due to male, female, veterans status or on the basis of disability.

Job

Job: R&D;

Primary Location: United States-California-Santa Clara

Other Locations: United States-California-Irvine

Organization: CCX

Schedule: Full-time

Job Posting: Apr 13, 2016, 6:35:00 PM

Unposting Date: Ongoing

Req ID: 160718