Kforce Principal Power and Signal Integrity Engineer in San Jose, California

Kforce's client, an established and growing Technology company in the San Jose, California (CA) metro area is seeking Senior Staff Signal and Power Integrity Engineer with a strong technical background and experience in signal and power integrity related essential duties and responsibilities.Essential Duties and Responsibilities:

  • Work with design engineers to provide design solutions for high-speed and low speed signals, clocks, power delivery signals, and power and ground planes

  • Provide routing guidelines for high-speed, low-speed, power signals, power and ground planes from bumps to balls

  • Thorough understanding of the SI and PI associated with bump signals/ground patterns and ability to optimize the balls signal/ground placement to improve the performance

  • Provide package layer counts, stack ups, materials, impedance control, test impedance targets, and optimizing net assignments for signals

  • Perform simulation/optimization to make sure critical signals meet their required specifications

  • Signal integrity analysis of frequency and time domain simulations for high speed signals and low speed signal following specifications

  • Optimize single ended or differential Insertion loss, Return loss, Xtlk, and power sum Xtlk for differential signaling groups and protocols

  • IR_DROP simulation for the power rails from bumps to balls

  • AC frequency sweep simulation to optimize the high RLC traces to the lower by achieving low resistance and inductance traces

  • Power plane resonance to measure the resonances of the package plans

  • PDN frequency domain and transient time domain analyses for PDN

  • Work as a team with other signal/power integrity engineers and design engineers to develop electrical design guidelines to optimize package designs

  • Bachelor's degree in Electrical Engineering

  • At least 5 years of relevant experience

  • Experience with IC package layout tools such as Cadence APD or SiP

  • Strong background in the application of Electromagnetics and High-Speed Transmission Line principles related to signal and power integrity

  • Knowledge of high-speed buss design compliance including DDR3, DDDR4, PCIE3, PCIe4, 10KR, 28 GBPS Ethernet PAM2 and 56 GBPS Ethernet PAM4

  • Proficiency in time and frequency domain modeling and use of 2D and 3D quasi-static and full-wave electromagnetic field solvers such as Cadence/Sigrity, Ansys, HFSS or ADS

  • Demonstrated and effective verbal/written communication skills

  • Excellent analytical and problem-solving skills

  • Great individual contributor and team player

  • Strong interpersonal skills to work professionally with our customers, global design & simulation teams and EDA tool vendors

  • Capable of determining component location, count, and specifications required to meet performance requirements

Preferred Qualifications:

  • Master's degree or PhD in Electrical Engineering

  • 5 years of experience is preferred

  • Track record of working successfully in cross-functional development teams across the globe

  • Familiarity with Outsourced Assembly and Test (OSAT) industry and understanding of substrate manufacturing and assembly processes

Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.Compensation Type:Years