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Apple ASIC Security Design Verification Engineer in Portland, Oregon

ASIC Security Design Verification Engineer

Portland, Oregon, United States

Hardware

  • Experience verifying security hardware.

  • Experience developing embedded system using low-level C and assembly.

  • Understanding of the SEI CERT C coding standard or similar practices.

  • Familiarity with all aspects of pre-silicon design verification.

  • History of building high quality UVM based verification environments.

  • Deep understanding of constrained random verification.

  • Knowledge of functional coverage.

  • Knowledge of assertion methodology.

  • Excellent interpersonal skills and the dream to face diverse challenges.

Description

As part of the security verification team you are at the heart of the chip design effort collaborating with all silicon engineering disciplines to get functional and secure products to millions of customers quickly. You will be responsible for ensuring the quality of the system-on-a-chip and are expected to architect testbenches, define methodology, develop firmware, coverage plans, test plans, tests. You will work with design and micro-architecture teams to understand the functional and performance goals of the project. You will evaluate design specs as they are written, conduct verification plan reviews, develop block level tests and triage failures. You will build bare-metal chip level tests as well as validate embedded firmware for security critical operations. Your diplomatic skills will be required to find collaborative approaches to resolve bugs you find while owning the verification efforts in your area of the design. You will also need to balance our team goals while coordinating engineering efforts across the diverse teams that use our hardware.

Education & Experience

MSEE, MSCE, BSEE, BSCS

Additional Requirements

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