Facebook Analog Layout Engineer in Menlo Park, California
Facebook's mission is to give people the power to build community and bring the world closer together. Through our family of apps and services, we're building a different kind of company that connects billions of people around the world, gives them ways to share what matters most to them, and helps bring people closer together. Whether we're creating new products or helping a small business expand its reach, people at Facebook are builders at heart. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities - we're just getting started.
Facebook Reality Labs, or FRL, focuses on delivering Facebook's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
As an Analog IC Layout Engineer at Facebook Reality Labs you will work with a world-class group of engineers creating high performance and area/power efficient custom layouts in advanced CMOS process nodes for our next generation, leading edge display driver ICs. You will work closely with circuit designers and the physical design team to define the IC floor-plan, chip partitioning and power distribution.
Deliver block level and macro level analog layout IPs based on circuit specifications, top level floor-plan and schedule
Participate in Macro level and SOC level floor-plan including power and signal distribution
Running physical verification like DRC/LVS/ERC and parasitic extraction at block level and macro level
Ability to develop skill codes/techniques necessary to improve productivity and reliability
Work with SOC physical design team to develop robust macro integration guidelines
Participate in process improvements
Able to complete any assigned layout task with minimal supervision
Ability to communicate clearly
Ability to travel both domestically and internationally up to 20% of the time
3+ years of experience as an IC Layout Designer with analog/mixed signal layout experience
Experience with layout techniques for device matching, noise isolation, electro-migration, power distribution, latch-up, ESD and high frequency circuits using state of the art deep sub-micron technologies including FinFET
Experience with Cadence layout tools and Mentor Verification tools (Virtuoso, VXL/GXL, Calibre)
Experience debugging and resolve LVS/DRC/ERC errors independently
Bachelor’s degree in EE or similar
Exposure to FinFET process technology and its constraints for analog layout techniques and qualities
Experience with standard cell layout and memory layout
Equal Opportunity: Facebook is proud to be an Equal Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Facebook is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at firstname.lastname@example.org.