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Apple Wireless PHY Design Verification Engineer in Cupertino, California

Wireless PHY Design Verification Engineer

Santa Clara Valley (Cupertino), California, United States

Hardware

  • 2+ years hands-on PHY verification experience.

  • Advanced knowledge of SystemC, TLM and Virtual prototyping, SystemVerilog and DV methodologies (problem solving, constrained random testing, SystemVerilog Assertion (SVA) and debugging).

  • Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.

  • Should be a team player with excellent communication skills and the desire to take on diverse challenges.

Description

• Experience with DSP design verification (e.g. digital filter, modulation, demodulation, frequency estimation, channel estimation, amplitude gain control etc.) • Understand PHY layer pipeline design, data-path bit-matching concept against golden reference model (Matlab or C) • Experience with mixed signal simulation (ADC, DAC, Power Amplifier, LNA etc.) using RF behavior model and digital PHY’s RTL is a plus. • Understand verification methodology (UVM/OVM etc.) • Good understanding on C/C++/Python, experience with C modeling for design verification (DPI, etc.) • Be able to craft crisp test plans for PHY keeping key DSP concepts in mind. • Be able to appropriately judge complexities of various PHY modules and overall data path. • Be able to do hands-on TB, Test development, debug, provide guidance to the team by calling priorities appropriately. • Have proven track record of delivering complex wireless chip with 0-spin tapeout success.

Education & Experience

Must have MS in Electrical Engineering with Signal Processing background and work experience in a signal processing chips (WiFi, BT, 3G, LTE modem)

Additional Requirements

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