Apple SoC Physical Design Verification Engineer in Cupertino, California
SoC Physical Design Verification Engineer
Santa Clara Valley (Cupertino),California,United States
You have 5-10 years of physical design experience, with emphasis on physical verification.
Strong knowledge of physical verification flows and methodology.
Knowledge of all aspects of ASIC physical design.
Scripting skills to debug flow related issues and make enhancements as appropriate.
Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
Real chip tapeout experience with a track record of successful signoff.
Layout design background and experience a plus.
As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level. You'll collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You'll work on padring, bump, RDL design, and working with the package and floorplan teams.
Education & Experience
You have a BSEE or MSEE.
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