Apple SoC Design Verification Engineer in Cupertino, California
SoC Design Verification Engineer
Santa Clara Valley (Cupertino),California,United States
Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy
Knowledge of Verilog/System Verilog, digital simulation and debug
Knowledge of computer architecture and digital design fundamentals
Ability to work independently to deliver the project goals
Exposure to UVM is desired
Experience with C/C++, assembly is a plus
Experience with perl, python or similar scripting language
Excellent interpersonal skills and the dream to take on diverse challenges
As part of a very talented team you will be at the heart of the chip design effort collaborating with all disciplines (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test effectively. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & test benches. It's required that you communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases. We also require additional responsibilities such as running and triaging regressions, tracking bugs, and analyzing coverage to achieve top results.
Education & Experience
BSEE or BSCS required; Master’s or PhD desired.
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