Apple Design Verification Engineer in Cupertino, California
Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Ten or more years of experience in a digital DV role
Track record as a great teammate who has taken several designs from the specification phase to successful tapeout
Accomplished in constrained random verification techniques
Accomplished in using object oriented programming techniques to develop reference models using System Verilog
Familiarity with one or more of the common verification frameworks (e.g. UVM, VMM, OVM)
Experience developing protocol checkers using System Verilog Assertions
Familiarity with clock domain crossing design and verification techniques
Experience running and debugging gate level simulations
Experience writing scripts in Perl, Python, or TCL
•Collaborate with architects in developing precise design specifications for digital control blocks in mixed signal designs. •Use design specifications to build block and chip level verification plans. •Architect block level verification environments, and assist in architecting and crafting chip and system level verification environments. •Use System Verilog and UVM to develop drivers, checkers, and reference models. •Debug regression failures. •Use functional and code coverage to track progress and gauge tapeout readiness.
Education & Experience
•Bachelor’s degree in electrical engineering or computer science; masters or higher preferred
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