Apple Design Verification Engineer in Cupertino, California
Design Verification Engineer
Santa Clara Valley (Cupertino),California,United States
Deep knowledge of System Verilog test-bench language and UVM
Proven experience developing scalable and portable test-benches
Proven experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
Experience with mixed signal verification methodology
In lieu of UVM knowledge, C/C++ expert knowledge
Significant experience with DDR PHY or Controller
Deep knowledge of one of the scripting languages: Python, Perl, TCL
Deep knowledge of formal verification methodology
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches. Track and report DV progress using a variety of metrics, including bugs and coverage. Develop mixed-signal simulation environment, and work closely with analog team to ensure overall bug-free mixed-signal designs.
Education & Experience
Masters + 3 years industrial experience Bachelors + 5 years industrial experience
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