Apple Design Verification Engineer in Cupertino, California
Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Advanced knowledge of standard ASIC design and verification flows including RTL design, simulation and testbench development
Solid verification skills in problem solving, constrained random testing, and debugging
Experience defining coverage space and writing coverage model a plus
Experience with SystemVerilog Assertion (SVA) a plus Team player with excellent communication skills and the desire to take on diverse challenges
Experience writing scripts in languages such as Perl or Python
Expertise in HVL and HDL (SystemVerilog, Verilog)
Advanced knowledge of HVL methodology (UVM/OVM)
Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development. Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage. Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model, and improve methodology. Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.
Education & Experience
BSEE/ or MSEE
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