Apple Design Verification Engineer in Cupertino, California
Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Strong knowledge in C/C++ based modeling in the domains of signal processing, system performance and memory management
Strong debugging skill using GDB and Valgrind
Experience with integrating model with Verilog, co-simulating and debugging in an integrated environment
Strong skill in modeling with floating point arithmetic, parametrized precision
Experience in defining and building modular architecture of a model based on a system architecture/design specifications
Work closely with the design team to review specifications and architecture, extract features, define modeling plan, framework Defining, building and debugging C/C++ based transaction level model Integrate model with the design and test benches and simulate with Verilog simulators Build model debug infrastructure using GDB/Valgrind or with Simulator
Education & Experience
BSEE/MSEE with 10+ years of relevant. PhD Preferred
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