Apple Design Verification Engineer in Cupertino, California
Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Deep knowledge of SystemVerilog test-bench language and UVM
Knowledge of RF Controller, PHY, and DFE
Experience developing scalable and portable test-benches
Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations
Experience with mixed signal verification methodology for IPs such as PHYs, PLLs, ADC, DAC etc.
Experience in verification using Verilog-AMS, wreal, SystemVerilog real, UDN models
Deep knowledge of SystemVerilog assertions
Deep knowledge of one of the scripting languages: Python, Perl, TCL
Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development. Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage. Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model, and improve methodology. Support mixed-signal co-simulation using Verilog models of analog IP.
Education & Experience
BSEE WITH 7+ YEARS OR MSEE WITH 5+ YEARS
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