Apple Design Verification Engineer – Media and Neural Engines in Cupertino, California
Design Verification Engineer – Media and Neural Engines
Santa Clara Valley (Cupertino),California,United States
Basic knowledge of computer architecture and digital design.
Knowledge of Verilog and Verilog simulators.
Should be a standout colleague who possess strong communication skills along with the dedication to undertake diverse challenges.
Knowledge of scripting languages such as Perl is a plus.
Experience with UVM or SystemVerilog for verification is a plus.
Knowledge or working experience with Media or Video processing is a plus.
Experience with industry standard interfaces is a plus.
Experience with hardware acceleration or Silicon debug is a plus.
Experience with low-level programming of complex computer systems in C/C++/assembly is a plus.
You will be responsible for ensuring the pre-silicon quality of key media processing hardware such as Apple’s Video and Display engines and Apple’s Neural Engine. Review architecture specifications to develop comprehensive test and coverage plans. Develop the verification environment and tests to implement test plans, using Object Oriented tools, in particular SystemVerilog and UVM. Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances. Triage and debug functional and performance issues with the design-under-test. Handle bug tracking and coverage convergence. Stay abreast with design specs, conduct test plan reviews, develop block, subsystem and full chip tests. Your demonstrated ability to work as a key member of a team, enabled by your ability to communicate with a broad audience will ensure you to thrive at Apple and successfully lead the verification efforts in a specific area of design. Work independently to align with the project goals and support multi-functional engineering efforts.
Education & Experience
BSEE / MSEE or MSCE
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