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Apple Design Verification Engineer - Entry Level in Cupertino, California

Design Verification Engineer - Entry Level

Santa Clara Valley (Cupertino),California,United States

Hardware

  • Extensive course work in digital design and computer architecture

  • Foundation in object oriented programming techniques

  • Lab courses or work experience with System Verilog

  • Familiar with constrained random verification techniques

  • Familiarity with clock domain crossing design and verification techniques

  • Some course work in analog circuit design

Description

-Collaborate in developing precise design specifications for digital control blocks -Use design specifications to create block and chip level verification plans. -Architect and create block level verification elements -Assist in architecting chip and system level verification environments. -Use System Verilog and UVM to develop drivers, tests, reference models and checkers -Debug test failures and work with designers to develop fixes -Use functional and code coverage to track progress and gauge tapeout readiness.

Education & Experience

  • Masters’ degree or higher in electrical engineering or computer science

Additional Requirements

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