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Apple Design Verification Engineer: Analog & Mixed Signal in Cupertino, California

Design Verification Engineer: Analog & Mixed Signal

Santa Clara Valley (Cupertino),California,United States


  • Do the following qualifications match your background? We usually look for at least 3 years of experience in industry for production integrated circuits.

  • Possess the ability to verify analog/mixed-signal designs in a collaborative work environment

  • Experience with developments in hardware descriptive languages: Verilog, System-Verilog, and/or Verilog-AMS code.

  • Having the capability to write analog assertion checks to catch bugs

  • Possess sufficient analog IC background to identify failure possibilities, work through first order debug, and analyze analog verification results

  • Ability to write test plans, present results, and communicate clearly with cross functional teams.

  • Submit simulation jobs through network computing clusters and manage both simulation clock and wall clock required to finish the verification plan.

  • We look for someone that understands both power management and related auxiliary circuitry: switching converters, linear converters, reference circuitry, band-gaps, data converters, and/or clock generators.

  • Have a familiarity with verification methodologies and tools: simulators, waveform viewers, execution automation, coverage collection, gate level simulations Experience developing scalable and portable test benches

  • A background that includes scripting or programming languages is preferred. These include, but are not limited to, TCL, Skill, Python, and/or PERL.

  • Your familiarity with analog behavioral models is also a plus.


In this role, you will be responsible for ensuring high quality silicon for IC chips and IPs. The workflow starts with careful review of specifications followed by crafting of a verification plan and schedule. Then the verification is executed according to plan to support tapeout. •Execution of verification plans from beginning to end: test bench and environment bring-up, regressions, failure debug, and tape-out •Develop detailed test and coverage plans based on IC specifications •Develop verification methodology suitable for the IP, ensuring scalability and portability •Develop verification environment, including stimuli, checkers, assertions, trackers, and coverage •Sign-off mixed signal designs in preparation for tapeout.

Education & Experience

•A master of science degree in electrical or computer engineering is preferred.

Additional Requirements

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