Qualcomm Low Power Design/Methodology Engineer(s) All levels - QCT, Cork, Ireland in Cork, Ireland

Job Description:

Job Id


Job Title

Low Power Design/Methodology Engineer(s) All levels - QCT, Cork, Ireland

Post Date




Qualcomm Technologies, Inc.

CDMA Technology at http://www.qualcomm.com/about/businesses/qct

Job Area

Engineering - Hardware


Ireland - Cork

Job Overview

  • Design low power / power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), on-chip sensor controller, digital power meter, and embedded voltage regulator controller.

  • 3rd party PHY IP landing, wrapper development and IP integration/enablement support

  • Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks.

  • Work closely with technology/circuit design team to close IP block specification/requirement.

  • Work closely with verification/physical design team to complete the IP design implementation.

  • Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows.

  • Work closely with system/software/test team to enable the low power feature in wireless SoC product.

  • Evaluate new low-power technologies and analyze their applications to address requirements.

  • Provide feedback for low-power chip and system architecture.

  • Understand and perform block & chip-level power analysis.

  • Understand and create block-level power models.

Minimum Qualifications

  • Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfil the principal duties of the role and possesses the required competencies.

Preferred Qualifications

  • Masters or PhD in Electrical or Computer Engineering

  • 3+ years of experience doing low power digital ASIC design.

  • Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding, simulation, synthesis, STA.

  • Previous experience in AVS (adaptive voltage scaling) desired.

  • Understanding of electrical engineering concepts, circuit analysis and logic design skills.

  • Familiarity with advanced low power techniques and high speed clocking desired.

  • Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as: Perl, Python, Tcl, and Make etc.

  • Strong knowledge with IEEE 1801 is a plus.

  • Good understanding of SoC architecture/micro-architecture.

  • Prefer to have SERDES PHY protocol knowledge and experience (USB2/USB3/PCIE/MIPI)

  • Strong debugging capabilities at simulation, emulation, and Silicon environments, including ability to design interesting debug experiments.

  • Collaborate closely with cross-function team to research, design and implement performance and power management strategy for product roadmap.

Education Requirements

Masters or PhD in Electrical or Computer Engineering


EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.