Cadence Design Systems, Inc. Lead Design Engineer in Bangalore, India

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Bachelors in Engineering with 5+ years of experience or Master’s with 4+ years of experience.

  • Strong background in mixed signal verification fundamentals, behavioral modelling, verification environment planning & development is a must.

  • Prior mixed signal verification experience in some of the serial bus protocol IP’s (PHY: USB /PCIE/DDR/DPHY/MPHY)

  • Experience in functional verification is an added plus.

  • Strong expertise in real number modelling using Verilog-AMS/SV.

  • Experience in PSL/SV assertions development

  • Strong RTL and GLS debug skills.

  • Should be process oriented and have a passion for scripting/automation

  • Good soft skills and experience of working collaboratively in cross site environment.

We’re doing work that matters. Help us solve what others can’t.

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. 
Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.