Apple SoC Design Verification Engineer in Austin, Texas
SoC Design Verification Engineer
Austin, Texas, United States
You are well-rounded in many aspects of verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy.
Knowledge of DRAM controller and LPDDR protocol is desirable.
Knowledge of Verilog/System Verilog, digital simulation and debug is required.
Exposure to UVM is desired.
Experience with low-level programming of computer systems in C and assembly is a plus.
Excellent teamwork with strong interpersonal skills and the eagerness to tackle diverse
In this highly visible role, you will be at the heart of the chip design effort collaborating with all disciplines. You will verify the functionality and performance of Apple’s best-in-class SOCs. You will review design and architecture specifications for next generation SOCs and IPs as you work closely with design & micro-architecture teams to understand the functional & performance goals of the design. Develop test plans, tests & coverage plans, define methodology & test benches. Implement block/full chip environments and test cases. Run regressions, handle bug tracking, analyze code & functional coverage. Work independently & lead deliverables to align with the project goals plus support multi-functional engineering efforts.
Education & Experience
BSEE or BSCS required, Master’s or PhD desired.
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